Wiring board design aiding apparatus, design aiding method, storage medium, and computer program

ABSTRACT

In a design aiding apparatus of the present invention, a plane clearance setting unit acquires information showing a predetermined margin, a component placement unit determines a placement area of a component such that, as seen in a lamination direction of a multilayer wiring board, at least one of the component and a pad connected to the component is included within a candidate area of a plane foil excluding a perimeter area, and a wiring unit determines a placement area of a wiring foil and a via in the same way that the placement area of the component is determined. Furthermore, in regard to a component, a component pad, a wiring foil, and a via whose placement areas have already been determined, a component placement inspection unit reports a design condition violation if the placement area of at least one of the component and the pad deviates outside the candidate area as seen in the lamination direction of the board, and a wiring inspection unit reports a design condition violation if the placement area of the wiring foil or the via deviates outside the candidate area as seen in the lamination direction of the board.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates generally to a design aidingapparatus, method, and computer program for aiding in a layout design ofelements on a multilayer wiring board. In particular, the presentinvention relates to technology that aids in the placement of theelements on the wiring board so as to reduce noise.

[0003] 2. Related Art

[0004] A prior art design aiding apparatus used in the layout design ofelements such as components, wiring foils, and vias on a multilayerwiring board (i) stores various design criterion information that showsmanufacturing restrictions relating to the processing of boards, themounting of components, and the like, (ii) automatically determines theplacement area of the various elements so as to comply with the designcriterion information, and (iii) reports when the placement area of anelement as indicated by a designer does not comply with the designcriterion information.

[0005] The design criterion information includes such information as (i)the minimum distance allowable between wiring foils, components,component pads (i.e. the connection area between wiring foil andcomponent), and via pads (i.e. the connection area between via andwiring foil), and (ii) the minimum distance allowable between thevarious wiring elements (i.e. wiring foils, components, component pads,via pads) and the edge of the board.

[0006]FIG. 27 shows an exemplary clearance information table 480provided in the prior art design aiding apparatus to store informationshowing the minimum distances described above. Table 480 has a firstclassification row 481, a second classification column 482, andclearance value cells 483 that store values showing the spacing to beprovided between the various elements given in row 481 and column 482.

[0007] In the prior art design aiding apparatus, the placement of wiringfoils, components, component pads, and via pads is determinedautomatically by component placement processing and wiring processing soas satisfy the minimum distances stored in clearance information table480.

[0008] The prior art design aiding apparatus also stores the minimumdistances required between the various layers of the board (i.e. thepower layer and the signal line layers provided above and below thepower layer) in order to achieve a predetermined level of noisereduction, and wiring is conducted automatically in accordance withthese stored minimum distances. The technology relating to the automaticwiring of multilayer wiring boards is disclosed in unexamined patentapplication publication 11-328235 “Pattern Automatic Wiring Method”filed in Japan.

[0009] Application of the prior art design aiding apparatus and theautomatic wiring method serves to reduce the workload required of thedesigner in the layout design of components, foils and other elements ona multilayer wiring board, and as a result, reductions in design timeand cost can be achieved.

[0010] However, research conducted in recent years into current flow inmultilayer wiring boards has revealed a previously unknown cause ofelectromagnetic interference (EMI). It is now known that EMI isincreased by current flowing through components, foils, and otherelements whose placement area, as seen in a lamination direction of theboard, overlaps with perimeter areas of the power plane and ground planehaving a predetermined margin. This is particularly true of current thathas a large high frequency component.

[0011] An effective means of reducing EMI caused by such current is toplace the various elements so that, as seen in the lamination directionof the board, they are included within an area of the power and groundplanes excluding a perimeter area having a predetermined margin.

[0012] This approach to reducing EMI is disclosed in Mark I. Montrose'sPrinted Wiring Board Design Techniques for EMC Compliance, IEEE Press,2^(nd) ed.2000, (order no. PC5816).

[0013] However, the prior art design aiding apparatus and automaticwiring method do not include design criterion information or designaiding capabilities that allow for the placement area of elements to bedetermined such that the elements, as seen in the lamination directionof the board, are included within an area of the power and ground planesexcluding a perimeter area.

[0014] In order to reduce the occurrence of EMI as described above, thedesigner is consequently required to manually determine the placement ofthe various elements, and as a result, the time and cost required inimplementing layout design that takes account of the effects of EMIcannot be reduced.

SUMMARY OF THE INVENTION

[0015] In view of the issues discussed above, an object of the presentinvention is to provide a design aiding apparatus, method, and computerprogram for aiding in the layout design of elements such as components,wiring foils, and vias on a multilayer wiring board so as to reduce theoccurrence of EMI.

[0016] (1) The stated object can be achieved by a design aidingapparatus that aids in a layout design of an element on a multilayerwiring board, the apparatus determining, when a placement area of aplane foil has been determined, a placement area of the element suchthat the element, as seen in a lamination direction of the board, isincluded within an area of the plane foil excluding a perimeter area.

[0017] According to this structure, the design aiding apparatusdetermines the placement area of elements, such as components, componentpads, wiring foils, and vias, to be within an area of the power planeand ground plane excluding a perimeter area of these planes as seen inthe lamination direction of the board, and as a result achieves layoutdesign that effectively reduces EMI.

[0018] Consequently, the designer is no longer required to manuallyadjust the placement area of the various elements in order to reduceEMI, and as a result reductions can be achieved in the time and costrequired in implementing layout design that takes account of EMI.

[0019] (2) Here, in regard to the apparatus described in section (1), acomponent and a pad, whose placement area is determined relative to aplacement area of the component, may be included as elements, and theapparatus may include: a plane foil placement information storage unitfor storing plane foil placement information showing a placement area ofa plane foil whose placement area has been determined; a plane clearanceinformation acquisition unit for acquiring plane clearance informationshowing one or more margins; and a component placement informationgeneration unit for determining the placement area of the component suchthat at least one of the component and the pad, as seen in thelamination direction of the board, is included within a first candidatearea of the plane foil excluding a perimeter area having a first marginshown in the plane clearance information, and for generating componentplacement information showing the determined placement area of thecomponent.

[0020] According to this structure, the design aiding apparatusdetermines the placement area of at least one of the component and thecomponent pads to be within an area of the power plane and ground planeexcluding a perimeter area of these planes as seen in the laminationdirection of the board, and as a result achieves the same effects asdescribed in section (1).

[0021] (3) Here, the apparatus described in section (2) may furtherinclude a signal attribute information acquisition unit for acquiringsignal attribute information showing an abruptness of a change over timeof a signal transmitted from or received by the component, and thecomponent placement information generation unit may include anabruptness judgment subunit for judging, based on the signal attributeinformation, whether the abruptness of the change over time of thesignal satisfies a predetermined condition, and generate componentplacement information only when the abruptness judgment subunit judgesin the affirmative.

[0022] According to this structure, the apparatus ensures thatcomponents handling high frequency signals (i.e. components particularlyprone to EMI) are placed within an area of the power and ground planesexcluding a perimeter area of these planes as seen in the laminationdirection of the board.

[0023] A prior art design aiding method may then be used in the layoutdesign of other components less prone to EMI, such that these othercomponents are placed in an area that includes the perimeter areas. As aresult, the apparatus achieves layout design that both reduces thelayout density of components and provides for effective EMI reduction.

[0024] (4) Here, in regard to the apparatus described in section (3),the signal attribute information may show at least one of a frequency, arise time, and a fall time of the signal, and the abruptness judgmentsubunit may judge in the affirmative if the frequency of the signal isgreater than or equal to a first threshold, or if at least one of therise time and the fall time of the signal is less than or equal to asecond threshold and a third threshold, respectively.

[0025] According to this structure, the same effects as described insection (3) can be achieved.

[0026] (5) Here, in regard to the apparatus described in section (2), aninclusive area may have been determined, with respect to the component,that includes the component and all pads whose placement area isdetermined relative to the placement area of the component, and thecomponent placement information generation unit may determine theplacement area of the component such that the inclusive area as seen inthe lamination direction of the board, is included within a secondcandidate area of the plane foil excluding a perimeter area having asecond margin shown in the plane clearance information, and generatecomponent placement information showing the determined placement area ofthe component.

[0027] According to this structure, the same effects as described insection (2) can be achieved.

[0028] (6) Here, in regard to the apparatus described in section (2),the component placement information generation unit may determine, whenplane foil placement information is not stored in the plane foilplacement information storage unit, the placement area of the componentsuch that at least one of the component and the pad, as seen in thelamination direction of the board, is included within an alternativecandidate area of a surface of the board excluding a perimeter areahaving a predetermined margin, and generate component placementinformation showing the determined placement area of the component.

[0029] According to this structure, design procedure restrictions aremitigated as a result of the design aiding apparatus determining theplacement area of components prior to the placement area of the powerand ground planes being determined, by presupposing the largest possiblearea for the placement of the power and ground planes.

[0030] (7) Here, in regard to the apparatus described in section (1), awiring foil and a via may be included as elements, and the apparatus mayinclude: a plane foil placement information storage unit for storingplane foil placement information showing a placement area of a planefoil whose placement area has been determined; a plane clearanceinformation acquisition unit for acquiring plane clearance informationshowing one or more margins; a wiring foil placement informationgeneration unit for determining a placement area of the wiring foil suchthat the wiring foil, as seen in the lamination direction of the board,is included within a first candidate area of the plane foil excluding aperimeter area having a first margin shown in the plane clearanceinformation, and for generating wiring foil placement informationshowing the determined placement area of the wiring foil; and a viaplacement information generation unit for determining a placement areaof the via such that the via, as seen in the lamination direction of theboard, is included within a second candidate area of the plane foilexcluding a perimeter area having a second margin shown in the planeclearance information, and for generating via placement informationshowing the determined placement area of the via.

[0031] According to this structure, the design aiding apparatusdetermines the placement area of the wiring foil and via to be within anarea of the power and ground planes excluding a perimeter area of theseplanes as seen in the lamination direction of the board, and as a resultachieves the same effects as described in section (1).

[0032] (8) Here, the apparatus described in section (7) may furtherinclude: a first signal attribute information acquisition unit foracquiring first signal attribute information showing an abruptness of achange over time of a first signal transmitted by the wiring foil; and asecond signal attribute information acquisition unit for acquiringsecond signal attribute information showing an abruptness of a changeover time of a second signal transmitted by the via, the wiring foilplacement information generation unit may include: a first abruptnessjudgment subunit for judging, based on the first signal attributeinformation, whether the abruptness of the change over time of the firstsignal satisfies a predetermined condition, and generate componentplacement information only if the first abruptness judgment subunitjudges in the affirmative, and the via placement information generationunit may include: a second abruptness judgment subunit for judging,based on the second signal attribute information, whether the abruptnessof the change over time of the second signal satisfies a predeterminedcondition, and generate component placement information only if thesecond abruptness judgment subunit judges in the affirmative.

[0033] According to this structure, the apparatus ensures thatcomponents handling high frequency signals (i.e. components particularlyprone to EMI) are placed within an area of the power and ground planesexcluding a perimeter area of these planes as seen in the laminationdirection of the board.

[0034] A prior art design aiding method may then be used in the layoutdesign of other components less prone to EMI, such that these othercomponents are placed in an area that includes the perimeter areas. As aresult, the apparatus achieves layout design that both reduces thelayout density of components and provides for effective EMI reduction.

[0035] (9) Here, in regard to the apparatus described in section (8),the signal attribute information may show at least one of a frequency, arise time, and a fall time of the first signal, and the first abruptnessjudgment subunit may judge in the affirmative if the frequency of thefirst signal is greater than or equal to a first threshold, or if atleast one of the rise time and the fall time of the first signal is lessthan or equal to a second threshold and a third threshold, respectively,and the signal attribute information may show at least one of afrequency, a rise time, and a fall time of the second signal, and thesecond abruptness judgment subunit may judge in the affirmative if thefrequency of the second signal is greater than or equal to the firstthreshold, or if at least one of the rise time and the fall time of thesecond signal is less than or equal to the second threshold and thethird threshold, respectively.

[0036] According to this structure, the same effects as described insection (8) can be achieved.

[0037] (10) Here, in regard to the apparatus described in section (7),the wiring foil placement information generation unit may furtherinclude a wiring possibility judgment subunit for judging whether it ispossible to determine the placement area of the wiring foil such thatthe wiring foil, as seen in the lamination direction of the board, isincluded within the first candidate area, the wiring foil placementinformation generation unit may determine, when the wiring possibilityjudgment subunit judges in the affirmative, the placement area of thewiring foil such that the wiring foil, as seen in the laminationdirection of the board, is included within the first candidate area, andgenerate wiring foil placement information showing the determinedplacement area of the wiring foil, and the wiring foil placementinformation generation unit may determine, when the wiring possibilityjudgment subunit judges in the negative, the placement area of thewiring foil such that, as seen in the lamination direction of the board,an overlap between the placement area of the wiring foil and theperimeter area of the plane foil having the first margin is small enoughto satisfy a predetermined condition, and generate wiring foil placementinformation showing the determined placement area of the wiring foil.

[0038] According to this structure, when the wiring foil cannot beplaced within an area excluding the perimeter area of the power andground planes as seen in the lamination direction of the board, theapparatus minimizes, as a next best option, the area of the wiring foiloverlapping with the perimeter area, and as a result achieves layoutdesign that reduces EMI.

[0039] (11) Here, in regard to the apparatus described in section (7),the wiring foil placement information generation unit may determine,when plane foil placement information is not stored in the plane foilplacement information storage unit, the placement area of the wiringfoil such that the wiring foil, as seen in the lamination direction ofthe board, is included within an alternative candidate area of a surfaceof the board excluding a perimeter area having a predetermined margin,and generate wiring foil placement information showing the determinedplacement area of the wiring foil, and the via placement informationgeneration unit may determine, when plane foil placement information isnot stored in the plane foil placement information storage unit, theplacement area of the via such that the via, as seen in the laminationdirection of the board, is included within the alternative candidatearea, and generate via placement information showing the determinedplacement area of the via.

[0040] According to this structure, design procedure restrictions aremitigated as a result of the design aiding apparatus determining theplacement area of components prior to the placement area of the powerand ground planes being determined, by presupposing the largest possiblearea for the placement of the power and ground planes.

[0041] (12) Here, in regard to the apparatus described in section (7), acomponent and a pad, whose placement area is determined relative to aplacement area of the component, can be further included as elements,and the apparatus may further include: a component placement informationgeneration unit for determining the placement area of the component suchthat at least one of the component and the pad, as seen in thelamination direction of the board, is included within a third candidatearea of the plane foil excluding a perimeter area having a third marginshown in the plane clearance information, and generating componentplacement information showing the determined placement area of thecomponent.

[0042] According to this structure, the design aiding apparatusdetermines the placement area of not only wiring foils and vias but alsocomponents and component pads to be within an area of the power andground planes excluding a perimeter area of these planes as seen in thelamination direction of the board, and as a result achieves the sameeffects as described in section (1).

[0043] (13) The stated object can also be achieved by a design aidingapparatus that aids in a layout design of an element on a multilayerwiring board, the apparatus reporting, when a placement area of theelement and a plane foil have been determined, a design conditionviolation if the placement area of the element, as seen in a laminationdirection of the board, deviates outside an area of the plane foilexcluding a perimeter area.

[0044] According to this structure, the apparatus reports a designcondition violation if the placement area of elements such ascomponents, component pads, wiring foils, and vias deviates outside anarea of the power and ground planes excluding a perimeter area as seenin the lamination direction of the board. Consequently, the designer isencouraged to make placement amendments, and as a result layout designthat effectively reduces EMI can be achieved.

[0045] (14) Here, in regard to the apparatus described in section (13),a component, whose placement area may have been determined, and a pad,whose placement area is determined relative to the placement area of thecomponent, may be included as elements, and the apparatus may include: acomponent placement information storage unit for storing componentplacement information showing the placement area of the component; aplane clearance information acquisition unit for acquiring planeclearance information showing one or more margins; a component deviationjudgment unit for judging, when the component has been placed inaccordance with the component placement information, whether theplacement area of at least one of the component and the pad, as seen inthe lamination direction of the board, deviates outside a firstcandidate area of the plane foil excluding a perimeter area having afirst margin shown in the plane clearance information; and a designcondition violation information generation unit for generating, when thecomponent deviation judgment unit judges in the affirmative, componentdesign condition violation information showing the component.

[0046] According to this structure, the apparatus reports a designcondition violation if the placement area of at least one of thecomponent and the component pads deviates outside an area of the powerand ground planes excluding a perimeter area of these planes as seen inthe lamination direction of the board. Consequently, the designer isencouraged to make placement amendments, and as a result layout designthat effectively reduces EMI can be achieved.

[0047] (15) Here, the apparatus described in section (14) may furtherinclude: a signal attribute information acquisition unit for acquiringsignal attribute information showing an abruptness of a change over timeof a signal transmitted from or received by the component, and thedesign condition violation information generation unit may include: anabruptness judgment subunit for judging, based on the signal attributeinformation, whether the abruptness of the change over time of thesignal satisfies a predetermined condition, and the design conditionviolation information generation unit may suppress the generation of thecomponent design condition violation information when the abruptnessjudgment subunit judges in the negative.

[0048] According to this structure, the apparatus reports a designcondition violation if the placement area of a component handling highfrequency signals (i.e. a component particularly prone to EMI) deviatesoutside an area of the power and ground planes excluding a perimeterarea as seen in the lamination direction of the board.

[0049] A prior art design aiding method may then be used to approve theplacement of components less prone to EMI within an area that includesthe perimeter areas. As a result, the apparatus achieves layout designthat both reduces the layout density of components and provides foreffective EMI reduction.

[0050] (16) Here, in regard to the apparatus described in section (14),an inclusive area may have been determined, with respect to thecomponent, that includes the component and all pads whose placement areais determined relative to the placement area of the component, and thecomponent deviation judgment unit may judge, when the component has beenplaced in accordance with the component placement information, whetherthe inclusive area, as seen in the lamination direction of the board,deviates outside a second candidate area of the plane foil excluding aperimeter area having a second margin shown in the plane clearanceinformation.

[0051] According to this structure, the same effects as described insection (14) can be achieved.

[0052] (17) Here, in regard to the apparatus described in section (14),the component deviation judgment unit may judge, when plane foilplacement information is not stored in the plane foil placementinformation storage unit, whether the placement area of at least one ofthe component and the pad, as seen in the lamination direction of theboard, deviates outside an alternative candidate area of a surface ofthe board excluding a perimeter area having a predetermined margin.

[0053] According to this structure, design procedure restrictions aremitigated as a result of the design aiding apparatus reporting anydeviation in a component placement that occurs prior to the placementarea of the power and ground planes being determined, by presupposingthe largest possible area for the placement of the power and groundplanes.

[0054] (18) Here, in regard to the apparatus described in section (13),a wiring foil and a via may be included as elements, the placement areasof which have been determined, and the apparatus may include: a wiringfoil placement information storage unit for storing wiring foilplacement information showing a placement area of the wiring foil; a viaplacement information storage unit for storing via placement informationshowing a placement area of the via; a plane foil placement informationstorage unit for storing plane foil placement information showing aplacement area of a plane foil whose placement area has been determined;a plane clearance information acquisition unit for acquiring planeclearance information showing one or more margins; a wiring foildeviation judgment unit for judging, when the wiring foil has beenplaced in accordance with the wiring foil placement information, whetherthe placement area of the wiring foil, as seen in the laminationdirection of the board, deviates outside a first candidate area of theplane foil excluding a perimeter area having a first margin shown in theplane clearance information; a via deviation judgment unit for judging,when the via has been placed in accordance with the via placementinformation, whether the placement area of the via, as seen in thelamination direction of the board, deviates outside a second candidatearea of the plane foil excluding a perimeter area having a second marginshown in the plane clearance information; and a design conditionviolation information generation unit for generating, when the wiringfoil deviation judgment unit judges in the affirmative, wiring foildesign condition violation information showing the wiring foil, and forgenerating, when the via deviation judgment unit judges in theaffirmative, via design condition violation information showing the via.

[0055] According to this structure, the apparatus reports a designcondition violation if the placement area of the wiring foil and viadeviates outside an area of the power and ground planes excluding aperimeter area as seen in the lamination direction of the board, and asa result achieves layout design that effectively reduces EMI.

[0056] (19) Here, the apparatus described in section (18) may furtherinclude: a first signal attribute information acquisition unit foracquiring first signal attribute information showing an abruptness of achange over time of a first signal transmitted by the wiring foil; and asecond signal attribute information acquisition unit for acquiringsecond signal attribute information showing an abruptness of a changeover time of a second signal transmitted by the via, and the designcondition violation information generation unit may include: a firstabruptness judgment subunit for judging, based on the first signalattribute information, whether the abruptness of the change over time ofthe first signal satisfies a predetermined condition; and a secondabruptness judgment subunit for judging, based on the second signalattribute information, whether the abruptness of the change over time ofthe second signal satisfies a predetermined condition, and the designcondition violation information generation unit may suppress thegeneration of the wiring foil design condition violation informationwhen the first abruptness judgment subunit judges in the negative, andsuppress the generation of the via design condition violationinformation when the second abruptness judgment subunit judges in thenegative.

[0057] According to this structure, the apparatus reports a designcondition violation if the placement area of a component handling highfrequency signals (i.e. a component particularly prone to EMI) deviatesoutside an area of the power and ground planes excluding a perimeterarea as seen in the lamination direction of the board.

[0058] A prior art design aiding method may then be used to approve theplacement of components less prone to EMI within an area that includesthe perimeter areas. As a result, the apparatus achieves layout designthat both reduces the layout density of components and provides foreffective EMI reduction.

[0059] (20) Here, in regard to the apparatus described in section (18),the design condition violation information generation unit may suppressthe generation of the wiring foil design condition violation informationwhen the wiring foil deviation judgment unit judges in the affirmative,and when the placement area of the wiring foil is such that, as seen inthe lamination direction of the board, an overlap between the placementarea of the wiring foil and the perimeter area of the plane foil havingthe first margin is small enough to satisfy a predetermined condition.

[0060] According to this structure, the apparatus suppresses thereporting of a design condition violation with respect to a wiring foilwhose placement area has been determined as a next best option when itwas not possible to place the wiring foil within an area of the powerand ground planes excluding a perimeter area as seen in the laminationdirection of the board, and as a result achieves layout design thatreduces EMI.

[0061] (21) Here, in regard to the apparatus described in section (18),the wiring foil deviation judgment unit may judge, when plane foilplacement information is not stored in the plane foil placementinformation storage unit, whether the placement area of the wiring foil,as seen in the lamination direction of the board, deviates outside analternative candidate area of a surface of the board excluding aperimeter area having a predetermined margin, and the via deviationjudgment unit may judge, when plane foil placement information is notstored in the plane foil placement information storage unit, whether theplacement area of the via, as seen in the lamination direction of theboard, deviates outside an alternative candidate area of a surface ofthe board excluding a perimeter area having a predetermined margin.

[0062] According to this structure, design procedure restrictions aremitigated as a result of the design aiding apparatus reporting anydeviation in a component placement that occurs prior to the placementarea of the power and ground planes being determined, by presupposingthe largest possible area for the placement of the power and groundplanes.

[0063] (22) Here, in regard to the apparatus described in section (18),a component, whose placement area may have been determined, and a pad,whose placement area is determined relative to the placement area of thecomponent, may be further included as elements, and the apparatus mayfurther include: a component placement information storage unit forstoring component placement information showing the placement area ofthe component; and a component deviation judgment unit for judging, whenthe component has been placed in accordance with the component placementinformation, whether the placement area of at least one of the componentand the pad, as seen in the lamination direction of the board, deviatesoutside a third candidate area of the plane foil excluding a perimeterarea having a third margin shown in the plane clearance information, andthe design condition violation information generation unit may generate,when the component deviation judgment unit judges in the affirmative,component design condition violation information showing the component.

[0064] According to this structure, the apparatus encourages thedesigner to make amendments to the layout design by reporting a designcondition violation if the placement area of not only the wiring foilsand vias but also the components and component pads deviates outside anarea of the power and ground planes excluding a perimeter area as seenin the lamination direction of the board, and as a result the apparatusachieves the same effects as described in section (13).

[0065] (23) The stated object can also be achieved by a design aidingmethod for aiding in a layout design of an element on a multilayerwiring board, the method including: a plane clearance informationacquisition step of acquiring plane clearance information showing one ormore margins; and a placement information generation step ofdetermining, when a placement area of a plane foil has been determined,a placement area of the element such that the element, as seen in alamination direction of the board, is included within a candidate areaof the plane foil excluding a perimeter area having a margin shown inthe plane clearance information, and of generating placement informationshowing the determined placement area of the element.

[0066] According to this structure, the same effects as described insection (1) can be achieved.

[0067] (24) The stated object can also be achieved by a design aidingmethod for aiding in a layout design of an element on a multilayerwiring board, the method including: a plane clearance informationacquisition step of acquiring plane clearance information showing one ormore margins; and a design condition violation information reportingstep of reporting, when a placement area of the element and a plane foilhas been determined, a design condition violation if the placement areaof the element, as seen in a lamination direction of the board, deviatesoutside a candidate area of the plane foil excluding a perimeter areahaving a margin shown in the plane clearance information.

[0068] According to this structure, the same effects as described insection (13) can be achieved.

[0069] (25) The stated object can also be achieved by a computer programexecuted by a design aiding apparatus that aids in a layout design of anelement on a multilayer wiring board, the computer program including: aplane clearance information acquisition step of acquiring planeclearance information showing one or more margins; and a placementinformation generation step of determining, when a placement area of aplane foil has been determined, a placement area of the element suchthat the element, as seen in a lamination direction of the board, isincluded within a candidate area of the plane foil excluding a perimeterarea having a margin shown in the plane clearance information, and ofgenerating placement information showing the determined placement areaof the element.

[0070] According to this structure, the same effects as described insection (1) can be achieved.

[0071] (26) The stated object can also be achieved by a computer programexecuted by a design aiding apparatus that aids in a layout design of anelement on a multilayer wiring board, the computer program including: aplane clearance information acquisition step of acquiring planeclearance information showing one or more margins; and a designcondition violation information reporting step of reporting, when aplacement area of the element and a plane foil has been determined, adesign condition violation if the placement area of the element, as seenin a lamination direction of the board, deviates outside a candidatearea of the plane foil excluding a perimeter area having a margin shownin the plane clearance information.

[0072] According to this structure, the same effects as described insection (13) can be achieved.

[0073] (27) The stated object can also be achieved by acomputer-readable storage medium storing a computer program executed bya design aiding apparatus that aids in a layout design of an element ona multilayer wiring board, the computer program including: a planeclearance information acquisition step of acquiring plane clearanceinformation showing one or more margins; and a placement informationgeneration step of determining, when a placement area of a plane foilhas been determined, a placement area of the element such that theelement, as seen in a lamination direction of the board, is includedwithin a candidate area of the plane foil excluding a perimeter areahaving a margin shown in the plane clearance information, and ofgenerating placement information showing the determined placement areaof the element.

[0074] According to this structure, the same effects as described insection (1) can be achieved.

[0075] (28) The stated object can also be achieved by acomputer-readable storage medium storing a computer program executed bya design aiding apparatus that aids in a layout design of an element ona multilayer wiring board, the computer program including: a planeclearance information acquisition step of acquiring plane clearanceinformation showing one or more margins; and a design conditionviolation information reporting step of reporting, when a placement areaof the element and a plane foil has been determined, a design conditionviolation if the placement area of the element, as seen in a laminationdirection of the board, deviates outside a candidate area of the planefoil excluding a perimeter area having a margin shown in the planeclearance information.

[0076] According to this structure, the same effects as described insection (13) can be achieved.

BRIEF DESCRIPTION OF THE DRAWINGS

[0077] These and other objects, advantages and features of the inventionwill become apparent from the following description thereof taken inconjunction with the accompanying drawings that illustrate specificembodiments of the present invention.

[0078] In the drawings:

[0079]FIG. 1 is a functional block diagram showing an overall structureof a design aiding apparatus 1000 according to an embodiment of thepresent invention;

[0080]FIG. 2 shows an exemplary command acquired by design aidingapparatus 1000;

[0081]FIG. 3 shows an exemplary content displayed on a display unit;

[0082]FIG. 4 is a top down view of planes, components, pads, wiringfoils, and vias as seen in a lamination direction of a wiring board;

[0083]FIG. 5 is a side view of the elements shown in FIG. 4;

[0084]FIG. 6 shows exemplary board information stored in boardinformation table 400;

[0085]FIG. 7 shows exemplary component master information stored incomponent master information table 410;

[0086]FIG. 8 shows exemplary component form information stored incomponent form information table 420;

[0087]FIG. 9 shows exemplary component information stored in componentinformation table 430;

[0088]FIG. 10 shows exemplary net information stored in net informationtable 440;

[0089]FIG. 11 shows exemplary component placement information stored incomponent placement information table 450;

[0090]FIG. 12 shows exemplary foil placement information stored in foilplacement information table 460;

[0091]FIG. 13 shows exemplary via placement information stored in viaplacement information table 470;

[0092]FIG. 14 shows exemplary plane clearance information stored inplane clearance information table 490;

[0093]FIG. 15 is a top down view of margins shown in the plane clearanceinformation;

[0094]FIG. 16 shows exemplary design condition violation informationstored in design condition violation information table 510;

[0095]FIG. 17 is a flowchart of a main routine of the processingconducted by design aiding apparatus 1000;

[0096]FIG. 18 is a flowchart of a plane clearance processing subroutine;

[0097]FIG. 19 is a flowchart of a plane placement processing subroutine;

[0098]FIG. 20 is a flowchart of a component placement processingsubroutine;

[0099]FIG. 21 is a flowchart of a wiring processing subroutine;

[0100]FIG. 22 is a flowchart of a component placement inspectionprocessing subroutine;

[0101]FIG. 23 is a flowchart of a wiring inspection processingsubroutine;

[0102]FIG. 24A is a top down view showing a situation in which it is notpossible to determine the placement area of the wiring foils to bewithin a wiring foil candidate area;

[0103]FIG. 24B is a top down view showing the use of an alternative areain the placement of the wiring foils;

[0104]FIG. 25 shows an exemplary plane clearance information table 520storing plane clearance information specific to each wiring surface;

[0105]FIG. 26 is a top down view of an area that includes a plurality ofplanes; and

[0106]FIG. 27 shows exemplary clearance information stored in aclearance information table 480;

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0107] A design aiding apparatus of the present invention is describedbelow with reference to the drawings. The design aiding apparatus aidsin a layout design of elements such as components, wiring foils, andvias on a multilayer wiring board so as to reduce the occurrence of EMI.

[0108] (1) When the placement area of a plane foil has been determined,the design aiding apparatus determines the placement areas of acomponent, a wiring foil, and a via such that the wiring foil, the via,and at least one of the component and component pads (i.e. padsconnecting the component and the wiring foil) are included within atarget placement area of the plane foil that is on a wiring surface ofthe multilayer wiring board other than the wiring surface on which theplane foil is placed, and which excludes, as seen in a laminationdirection of the board, a perimeter area of the plane foil having apredetermined margin.

[0109] (2) Furthermore, with respect to a component, a wiring foil, anda via whose placement areas have been determined, the apparatus reportsa design condition violation if the placement area of the wiring foil,the via, and at least one of the component and component pads deviatesoutside the target placement area.

[0110] Here, a “plane foil” is a conductive foil of a predetermined sizethat is placed as a sheet on a wiring surface of the board, and is to bedistinguished from a “wiring foil” which is a conductive foil placed asa line on a wiring surface of the board.

[0111] Structure of the Design Aiding Apparatus

[0112]FIG. 1 is a functional block diagram showing an overall structureof a design aiding apparatus 1000 according to an embodiment of thepresent invention. Design aiding apparatus 1000 includes an input unit1010, a control unit 1020, a display unit 1030, a design informationaccess unit 1040, a design information memory unit 1050, a planeclearance setting unit 1100, a plane placement unit 1200, a componentplacement unit 1300, a wiring unit 1400, a component placementinspection unit 1500, and a wiring inspection unit 1600.

[0113] Specifically, design aiding apparatus 1000 is realized byhardware such as a processor, a read only memory (ROM) storing acomputer program, a working random access memory (RAM), and a hard diskdevice. The functions of apparatus 1000 described above are realized bythe processor executing the computer program stored in the ROM. Transferof information around the elements of apparatus 1000 is conducted viathe RAM and the hard disk device.

[0114] Input Unit 1010

[0115] Unit 1010 acquires, from an external source, command informationshowing operating instructions pertaining to design aiding apparatus1000, and outputs the acquired information to control unit 1020.

[0116]FIG. 2 shows exemplary command information 200 acquired by unit1010. Command information 200 includes a command classification column201 showing the various processing performed in design aiding apparatus1000, and a parameter column 202 showing the detailed objects of theprocessing. A full description of examples 203 to 210 will be given in alater section.

[0117] Control Unit 1020

[0118] Unit 1020 acquires the command information from input unit 1010,and in accordance with the command classification included in theacquired command information, instructs one of units 1100, 1200, 1300,1400, 1500, and 1600 to execute processing. Unit 1020 then transfers theparameters included in the command information to the unit instructed toexecute processing.

[0119] Display Unit 1030

[0120] On receipt of a processing instruction from control unit 1020,unit 1030 displays the placement status of components, wiring foils, andvias based on design information stored in design information storageunit 1050.

[0121]FIG. 3 shows an exemplary display 100 executed by unit 1030.

[0122] In display area 120, the placement status of the components,pads, wiring foils, vias, and the plane are shown from above as seen inthe lamination direction of the wiring board. The two white rectanglesin display area 120 are components, the plurality of oval shapesdepicted on either side of the components are pads connecting thecomponents with the wiring foils, the two white circles are vias, thetwo lines are wiring foils connecting the vias and the pads, and thegray rectangle is the plane. The different shapes are displayed usingvarious colors, degrees of brightness, line forms, and the like, so asto identify the different wiring surfaces on which the components, pads,wiring foils, vias, and planes are situated. Also displayed in displayarea 120 is a cursor that is controlled by a pointing device. The crossmark in display area 120 represents the cursor.

[0123] Display area 110 shows the XY coordinates of the center point ofthe cursor as well as numbers representing the wiring surfaces beingdisplayed.

[0124] For the purpose of confirmation, display area 130 shows thecommand acquired by input unit 1010.

[0125] Placement Target Elements

[0126] The planes, components, pads, wiring foils, and vias targeted forlayout design using design aiding apparatus 1000 will now be describedwith reference to FIGS. 4 and 5. In addition, the method of indicatingthe placement area of a placement target element will also be described.

[0127]FIG. 4 is a top down view of the planes, components, pads, wiringfoils, and vias as seen in the lamination direction of the board. FIG. 5is a side view of the elements shown in FIG. 4.

[0128] Wiring Board

[0129] A wiring board 310 given as an example in FIGS. 4 and is amultilayer wiring board having four wiring surfaces. In FIG. 5 theposition and ID numbering of the wiring surfaces is indicated by thebroken lines and the numbers to the left of the broken lines.

[0130] Design aiding apparatus 1000 shows the placement area of theplacement target elements using a three dimensional orthogonalcoordinate system, where the wiring surfaces of the wiring boardcorrespond to the XY plane and the lamination direction of the board isin a Z direction.

[0131] Plane

[0132] In FIGS. 4 and 5, 360 and 361 are exemplary planes. Planes 360and 361 are placed respectively in sheet-form in the rectangular areasshown in FIG. 4 on the third wiring surface.

[0133] In apparatus 1000, the placement area of the planes is indicatedby the number of the wiring surface as well as the XY coordinates of thevertices of the respective placement areas. Apparatus 1000 recognizes anarea (not marked in the drawings) of each plane excluding a perimeterarea having a predetermined margin as candidate areas for placement.

[0134] Component

[0135] Each component includes one or more pins. Each pin is connectedto a pad on either the front or back surfaces of the wiring board. Here,a pad connected to a component is referred to as a “component pad”. Eachcomponent pad is a section of the conductive foil laid over at least oneof the front and back surfaces of the wiring board. Apparatus 1000manages each component pad jointly with the component to which it isconnected.

[0136] Referring to FIG. 4, in apparatus 1000 each component is brokendown into four areas.

[0137] 1) a component pad area: the area of the pads connected to thecomponent

[0138] 2) a main body area: the smallest rectangular area containing thecomponent

[0139] 3) an inclusive area: the smallest rectangular area containingthe component and the component pads

[0140] 4) an offset area: an area larger than the inclusive area by apredetermined margin and which is provided so as to enable wiring to berouted without interference from adjacent components

[0141] In FIGS. 4 and 5, 321 and 331 are components, 322 and 332 arepins, 323 and 333 are component pads, 324 and 334 are main body areas,325 and 335 are inclusive areas, and 328 and 338 are offset areas.

[0142] The determined placement area of a component is indicated inapparatus 1000 as follows:

[0143] 1) A reference point is determined that is fixed in relation tothe main body of the component.

[0144] 2) A reference direction is determined that is also fixed inrelation to the main body of the component.

[0145] 3) A placement surface (i.e. the front or back surface of thewiring board), a placement point (i.e. an XY coordinate on the selectedplacement surface), and a placement angle (i.e. the angle between the Xaxis and the reference direction of the component placed such that thereference point is aligned with the XY coordinate of the placementpoint) are then specified.

[0146] The placement area of a component on a wiring board is indicatedas described above. In FIG. 4, 326 marks the reference point andreference direction of component 321, and 327 marks the placement angle.

[0147] Via

[0148] A via is a conductor placed so as to pass through an insulatorthat lies between any two wiring surfaces. Both ends of the via connectwith pads positioned on the wiring surfaces. Here, a pad connected to avia is referred to as a “via pad”. The via either fills a thru-holeprovided between the two wiring surfaces or is applied/plated to theinner surface of the thru-hole. A via pad is a wiring foil laid on awiring surface so as to be concentric with the thru-hole. Apparatus 1000manages each via pad jointly with the via to which it is connected.

[0149] In FIGS. 4 and 5, 351 is a via pad connected to a via and 352 isa thru-hole in which the via is placed.

[0150] In design aiding apparatus 1000, the placement area of a via isindicated by the number of the wiring surfaces (i.e. 1, 2, 3, 4) onwhich both ends of the via are positioned, the XY coordinates of thecenter of the thru-hole, and the diameter of the via pads to which thevia is connected.

[0151] Wiring Foil

[0152] A wiring foil is a conductive foil laid in a placement areahaving a certain width on the wiring surface on which it is placed. Eachwiring foil is connected collectively to a component pad, a via pad, anda plane.

[0153] In FIG. 4, 341 and 342 are wiring foils (only wiring foil 342 isshown in FIG. 5).

[0154] In apparatus 1000, the placement area of a wiring foil isindicated by the width of the placement area, the XY coordinates of bothends of the wiring foil, and the XY coordinates of any points throughwhich the wiring foil passes.

[0155] Design Information Unit 1040

[0156] Unit 1040 receives predetermined design information from units1100, 1200, 1300, and 1400, and stores the received design informationin design information memory unit 1050. Furthermore, on receipt of arequest for design information from any of units 1030, 1100, 1200, 1300,1400, 1500, and 1600, design information unit 1040 acquires therequested design information from design information memory unit 1050and transfers the acquired design information to the unit that sent therequest.

[0157] Design Information Memory Unit 1050

[0158] Unit 1050 includes the tables described below, and storespredetermined design information in the tables. The tables included inunit 1050 as well as the design information they store will now bedescribed in detail.

[0159] Board Information Table 400

[0160]FIG. 6 shows exemplary board information stored in table 400.Table 400 has a structural points column 401 and a column 402 showingthe number of wiring surfaces.

[0161] Column 401 stores the XY coordinates of the vertices of thewiring board, and column 402 stores the total number of wiring surfacesincluded in the board.

[0162] The board information stored in table 400 is provided in advanceto apparatus 1000 from an external circuit design aiding apparatus, adesign information maintenance apparatus, or the like.

[0163] Component Master Information Table 410

[0164]FIG. 7 shows exemplary component master information stored intable 410.

[0165] Table 410 has an ID name column 411, a type column 412, a column413 showing the number of pins, and a form column 414.

[0166] Column 411 stores names identifying the components. Column 412stores symbols indicating the various component types (eg. IC,capacitor). Column 413 stores the total number of pins included in eachcomponent. Column 414 stores information identifying the various formsof the components.

[0167] The component master information stored in table 410 is providedin advance to apparatus 1000 from an external circuit design aidingapparatus, a design information maintenance apparatus, or the like.

[0168] Component Form Information Table 420

[0169]FIG. 8 shows exemplary component form information stored in table420. Table 420 has a form column 421, a main body area column 422, a pinnumber column 423, a component pad area column 424, an inclusive areacolumn 425, and an offset area column 426.

[0170] Column 421 stores information showing the various forms of thecomponents. Column 422 stores the XY coordinates of the opposite anglesof the main body area of components placed such that the reference pointis aligned with the XY coordinate of the origin and the referencedirection is aligned with the X axis (hereafter, this placement methodis referred to as “reference placement”). Column 423 stores numbersidentifying each of the pins included in the components. Column 424stores the XY coordinates of the opposite angles of the component padarea of component pads connected to the pins of components that havebeen placed in accordance with reference placement. Column 425 storesthe XY coordinates of the opposite angles of the inclusive area of thecomponents. Column 426 stores the XY coordinates of the opposite anglesof the offset area of the scomponents.

[0171] The component form information stored in table 420 is provided inadvance to apparatus 1000 from an external circuit design aidingapparatus, a design information maintenance apparatus, or the like.

[0172] Component Information Table 430

[0173]FIG. 9 shows exemplary component information stored in table 430.

[0174] Table 430 has an ID name column 431, a classification column 432,a component pad clearance column 433, a component clearance value column434, an inclusive area clearance column 435, and an offset areaclearance column 436.

[0175] Column 431 stores names identifying the components. Column 432stores names identifying the various classifications of the components.Columns 433, 434, 435, and 436 store the allowable margins between theedge of the plane and the component pad area, the main body area, theinclusive area, and the offset area, respectively, when these marginshave been regulated for each component.

[0176] The component information stored in table 430 is provided inadvance to apparatus 1000 from an external circuit design aidingapparatus, a design information maintenance apparatus, or the like.

[0177] Net Information Table 440

[0178]FIG. 10 shows exemplary net information stored in table 440.

[0179] Table 440 has a net ID name column 441, a pin ID column 442, afrequency column 443, a rise time column 444, a fall time column 445, atype column 446, a wiring foil clearance column 447, a via pad clearancecolumn 448, and a foil width column 449.

[0180] Column 441 stores names identifying the nets. Column 442 storesnames identifying the pins included in components belonging to the nets.Columns 443, 444, and 445 store respectively the maximum value of thefrequencies, and the minimum value of the rise times and fall times whenthese values have been regulated with respect to the signals flowingthrough the nets. Column 446 stores names identifying the type ofsignals flowing through the nets (eg. clock signal, general signal,ground signal). Columns 447 and 448 store respectively the allowablemargins between the edge of a plane and the wiring foils and via padsbelonging to the net when these margins have been regulated with respectto each net. Column 449 stores the width of wiring foils belonging tothe nets.

[0181] The net information stored in table 440 is provided in advance toapparatus 1000 from an external circuit design aiding apparatus, adesign information maintenance apparatus, or the like.

[0182] Component Placement Information Table 450

[0183]FIG. 11 shows exemplary component placement information stored intable 450.

[0184] Table 450 has an ID name column 451, a placement surface column452, a placement point column 453, and a placement angle column 454.

[0185] Column 451 stores names identifying the components. Column 452stores numbers showing the wiring surface on which the components areplaced. Column 453 stores XY coordinates showing the position with whichthe reference point of components is to be aligned. Column 454 storesthe angle between the X axis and the reference direction of thecomponents.

[0186] The component placement information stored in table 450 isgenerated by component placement unit 1300 and transferred to designinformation storage unit 1050 via design information access unit 1040.

[0187] Foil Placement Information Table 460

[0188]FIG. 12 shows exemplary foil placement information stored in table460.

[0189] Table 460 has a foil ID name column 461, a net ID name column462, a placement surface column 463, a form type column 464, a placementpoint column 465, and a foil width column 466.

[0190] Column 461 stores names identifying the wiring foils or planes.Column 462 stores names identifying the net to which the wiring foils orplanes belongs. Column 463 stores numbers showing the wiring surface onwhich wiring foils or planes are placed. Column 464 stores namesindicating whether the foil is a wiring foil or a plane. Column 465stores either the XY coordinates of both ends of the wiring foils andany points through which the wiring foils pass, or the XY coordinates ofthe vertices of the placement area of the planes. Column 466 stores thewidth of the wiring foils when the width is regulated with respect toeach wiring foil.

[0191] The foil placement information stored in table 460 is generatedby plane placement unit 1200 and wiring unit 1400.

[0192] So as to distinguish foil placement information showing theplacement of wiring foils from foil placement information showing theplacement of planes, the former may alternatively be referred to as“routing information”.

[0193] Via Placement Information Table 470

[0194]FIG. 13 shows exemplary via placement information stored in table470.

[0195] Table 470 has a via ID name column 471, a net ID name column 472,a placement point column 473, a first placement surface column 474, asecond placement surface column 475, a hole diameter column 476, and avia diameter column 477.

[0196] Column 471 stores names identifying the vias. Column 472 storesnames identifying the net to which the vias belong. Column 473 storesthe XY coordinate of the central position of the vias. Columns 474 and475 store the number of the wiring surfaces on which both ends of thevias are placed. Column 476 stores the diameter of the thru-holesthrough which the vias are mounted. Column 477 stores the diameter ofthe pads to which the vias are connected.

[0197] The foil placement information stored in table 470 is generatedby wiring unit 1400.

[0198] Plane Clearance Information Table 490

[0199]FIG. 14 shows exemplary plane clearance information stored intable 490.

[0200] Table 490 has a target element column 491 and a plane clearancecolumn 492.

[0201] Column 491 stores names showing target elements and areas. Column492 stores the allowable margins between each of the target elementsshown in column 491 and the edge of the plane. Cells 493 to 498 store,respectively, a component pad clearance value, a component pad clearancevalue, a component clearance value, an inclusive area clearance value,an offset area clearance value, a wiring foil clearance value, and a viapad clearance value.

[0202] These values apply to all components and nets except those shownin component information table 430 and net information table 440 whoseclearance value is regulated individually.

[0203] The plane clearance information stored in table 490 is generatedby plane clearance setting unit 1100.

[0204]FIG. 15 is a top down view of the margins shown in the planeclearance information.

[0205] In FIG. 15, 501 is a plane, and 503 to 508 are, respectively, thecomponent pad clearance value, the component clearance value, theinclusive area clearance value, the offset area clearance value, thewiring foil clearance value, and the via pad clearance value.

[0206] Design Condition Violation Information Table 510

[0207]FIG. 16 shows exemplary design condition violation informationstored in table 510.

[0208] Table 510 has an ID name column 511 and a target element column512.

[0209] Column 511 stores names identifying components, wiring foils, andvias. Column 512 stores names showing target elements and areas that donot comply with respective plane clearance values.

[0210] The design condition violation information stored in table 510 isgenerated by component placement inspection unit 1500 and wiringinspection unit 1600.

[0211] Processing Conducted by Design Aiding Apparatus 1000

[0212] The processing conducted by apparatus 1000 will now be describedwith reference to the flowcharts.

[0213]FIG. 17 is a flowchart of a main routine of the processingconducted by design aiding apparatus 1000.

[0214] Step S101: Input unit 1010 acquires command information from anexternal source and transfers the acquired information to control unit1020.

[0215] Step S102: Control unit 1020 analyses the transferred commandinformation, and if the information shows a plane clearance settingcommand, control unit 1020 proceeds to step s120.

[0216] Step S104: Alternatively, if the information shows a planeplacement command, control unit 1020 proceeds to step s150.

[0217] Step S106: Alternatively, if the information shows a componentplacement command, control unit 1020 proceeds to step s200.

[0218] Step S107: Alternatively, if the information shows a wiringcommand, control unit 1020 proceeds to step s300.

[0219] Step S108: Alternatively, if the information shows a componentplacement inspection command, control unit 1020 proceeds to step s400.

[0220] Step S109: Alternatively, if the information shows a wiringinspection command, control unit 1020 proceeds to step s500.

[0221] Step S110: Alternatively, if the information shows a completioncommand, control unit 1020 returns to step s101 and repeats theprocessing.

[0222] Step S120: Plane clearance unit 1100 conducts plane clearancesetting processing.

[0223] Step S150: Plane placement unit 1200 conducts plane placementprocessing.

[0224] Step S200: Component placement unit 1300 conducts componentplacement processing.

[0225] Step S300: Wiring unit 1400 conducts wiring processing.

[0226] Step S400: Component placement inspection unit 1500 conductscomponent placement inspection processing.

[0227] Step S500: Wiring inspection unit 1600 conducts wiring inspectionprocessing.

[0228] Step S600: Display unit 1030 displays the most up-to-dateplacement status of the planes, components, wiring foils, and vias shownby the design information stored in design information storage unit 1050in steps s120 through s500.

[0229] Display unit 1030 displays the components, wiring foils, and viasshown in the design condition violation information stored in table 510(FIG. 16) with bright/flashing illumination or specified colors so as tonotify the designer of a design condition violation. This display isconducted especially after the completion of the component placementinspection processing and the wiring inspection processing as a resultof which the design condition violation information is stored in table510.

[0230] The subroutines of each of the above processing operations willnow be described.

[0231] Plane Clearance Setting Processing

[0232] Plane clearance setting unit 1100 is mobilized by control unit1020 when the information acquired by input unit 1010 shows a planeclearance setting command. In this case, unit 1100 receives from controlunit 1020 the parameters included in the command information, andexecutes the plane clearance setting processing based on the receivedparameters.

[0233] In FIG. 2, cells 203 to 205 show, respectively, exemplaryformations 1, 2, and 3 of the parameters transferred to plane clearanceunit 1100 by control unit 1020.

[0234] The formation 1 parameters include in the stated order, acomponent pad clearance value, a component clearance value, an inclusivearea clearance value, an offset area clearance value, a wiring foilclearance value, and a via pad clearance value. These parameters show apredetermined clearance value allowable between the edge of a plane and,respectively, the component pads, main body of the component, inclusivearea, offset area, wiring foils, and via pads.

[0235] The formation 2 parameters include in the stated order, acomponent ID name, a component pad clearance value, a componentclearance value, an inclusive area clearance value, and an offset areaclearance value. These parameters are used for the component identifiedby the component ID name when the values specified in formation 2 differfrom those in formation 1.

[0236] The formation 3 parameters include in the stated order, a net IDname, a wiring foil clearance value, and a via pad clearance value.These parameters are used for the wiring foils and vias belonging to thenet identified by the net ID name when the values specified in formation3 differ from those in formation 1.

[0237]FIG. 18 is a flowchart of the plane clearance setting processingsubroutine.

[0238] Step S121: Plane clearance setting unit 1100 proceeds to eitherof steps s122, s123, or s124 depending on the specified formation of theparameters.

[0239] Step S122: When the formation 1 parameters are specified, planeclearance setting unit 1100 stores the clearance values included in theformation 1 parameters in the respective rows of plane clearanceinformation table 490 (FIG. 14).

[0240] Step S123: When the formation 2 parameters are specified, unit1100 stores, in component information table 430 (FIG. 9), the clearancevalues included in the formation 2 parameters in the respective columnsof the row of table 430 corresponding to the component ID name specifiedin the parameters.

[0241] Step S124: When the formation 3 parameters are specified, unit1100 stores, in net information table 440 (FIG. 10), the clearancevalues included in the formation 3 parameters in the respective columnsof the row of table 440 corresponding to net ID name specified in theparameters.

[0242] Plane Placement Processing

[0243] Plane placement unit 1200 is mobilized by control unit 1020 whenthe information acquired by input unit 1010 shows a plane placementcommand. In this case, unit 1200 receives from control unit 1020 theparameters included in the command information, and executes the planeplacement processing based on the received parameters.

[0244] In FIG. 2, cell 206 shows exemplary parameters transferred toplane placement unit 1200 by control unit 1020. The transferredparameters include in the stated order, a foil ID name, a net ID name, awiring surface number, and coordinates marking the vertices of the areaof the plane.

[0245]FIG. 19 is a flowchart of the plane placement processingsubroutine.

[0246] Step S151: Plane placement unit 1200 generates foil placementinformation showing the form of the plane, and in which is included thefoil ID name, net ID name, wiring surface, and placement pointsspecified in the parameters.

[0247] Step S152: Unit 1200 stores the generated foil placementinformation in table 460 (FIG. 12) via design information access unit1040.

[0248] Component Placement Processing

[0249] Component placement unit 1300 is mobilized by control unit 1020when the information acquired by input unit 1010 shows a componentplacement command. In this case, unit 1300 receives from control unit1020 the parameters included in the command information, and executesthe component placement processing based on the received parameters.

[0250] In FIG. 2, cell 207 shows exemplary parameters transferred tocomponent placement unit 1300 by control unit 1020. The transferredparameters include in the stated order, an area type and one or morecomponent ID names. The area type of the component pad area, the mainbody area, the inclusive area, and the offset area is specified usingthe numbers 1, 2, 3, and 4, respectively.

[0251]FIG. 20 is a flowchart of the component placement processingsubroutine.

[0252] Step S201: Component placement unit 1300 selects one of thecomponent ID names specified in the parameters.

[0253] Step S202: Unit 1300 retrieves from table 440 (FIG. 10), netinformation showing the pin ID names corresponding to the selectedcomponent ID name. Unit 1300 also retrieves from table 440, netinformation showing a frequency greater than or equal to a firstthreshold, a rise time less than or equal to a second threshold, and afall time less than or equal to a third threshold.

[0254] The first, second, and third thresholds are provided in advanceto apparatus 1000 from an external source and stored in a memory unit(not shown in the drawings).

[0255] By way of example, let the selected component ID be “IC1”, andthe first, second, and third thresholds be 30 MHz, 1.4 ns, and 1.35 ns,respectively. As such, net information corresponding to the net ID name“clk1” is retrieved from a search of table 440.

[0256] Step S203: If net information is not retrieved from the search oftable 440, unit 1300 proceeds to step s217.

[0257] Step S204: On the other hand, if net information is retrieved,unit 1300 searches table 460 (FIG. 12) for foil placement informationshowing the form type as “plane”.

[0258] Step S205: If foil placement information showing “plane” is notretrieved from the search, unit 1300 proceeds to step s206.

[0259] Step S206: Unit 1300 assumes that the form type is “plane” andthat foil placement information showing the coordinates of a placementarea of the plane (i.e. within an area of the wiring board surfaceexcluding a perimeter area having a predetermined margin) was retrievedfrom the search of table 460.

[0260] The coordinates of the placement area of the plane shown in theassumed foil placement information are calculated as follows. Unit 1300acquires the coordinates of the board stored in structural point column401 of board information table 400 (FIG. 6). Unit 1300 also acquires,from clearance information table 480 (FIG. 27) as the predeterminedmargin, the clearance value to be maintained between the component andthe edge of the board. Unit 1300 then shifts, by an amount equal to theacquired clearance value, the points of the acquired coordinates to bewithin an area marked by lines connecting each of the acquiredcoordinate points, and calculates the coordinates of the shifted points.The calculated coordinates show the vertices of the placement area ofthe plane.

[0261] Step S207: Unit 1300 acquires from table 430 (FIG. 9) componentinformation corresponding to the selected component ID name (i.e. “IC1”in the given example).

[0262] Depending on whether the area type specified in the parameters is1, 2, 3, or 4, unit 1300 then selects, respectively, the component padclearance value, the component clearance value, the inclusive areaclearance value, or the offset area clearance value included in theacquired component information.

[0263] If the relevant clearance values are not specified in theacquired component information, unit 1300 acquires clearance values fromtable 490 (FIG. 14) and selects the clearance value corresponding to thearea type specified in the parameters.

[0264] Unit 1300 then shifts, by an amount equal to the selectedclearance value, the points of either the coordinates included in theretrieved foil placement information or the coordinates calculated instep S206 to be within an area marked by lines connecting each of thepoints, and calculates the coordinates of the shifted points. Unit 1300recognizes the area marked by lines connecting each of the calculatedpoints as the candidate area of the component.

[0265] Step S208: Depending on the area type included in the parameter,unit 1300 executes one of steps s210, s211, and s212.

[0266] Step S209: Unit 1300 searches for a component placement area inwhich the component pad area of the component identified by the selectedcomponent ID name (i.e. “IC1”) is included within the recognizedcandidate area.

[0267] This processing operation may be conducted, for example, asfollows. First, unit 1300 uses a method applied by a prior art designaiding apparatus to determine the component placement area. Thedetermined placement area is shown by the XY coordinate of the placementpoint of the component, as well as by the angle (i.e. placement angle)between the X axis and the reference direction. Here, the determinedplacement area satisfies the clearance values shown in table 480 (FIG.27), although no consideration has been given to the margin between thecomponent placement area and the edge of the plane.

[0268] Next, unit 1300 judges whether the component pad area of thecomponent placed according to the determined placement point andplacement angle are included within the recognized candidate area.

[0269] If judged in the negative, unit 1300 calculates the size in theXY direction of the section of the component pad area deviating outsidethe candidate area. Then, so as to eliminate the deviation, unit 1300then either (i) shifts the placement point by an amount greater than orequal to the calculated size of the deviating section, (ii) amends theplacement angle, or (iii) amends both the placement point and angle.

[0270] If the component placed in accordance with the amended placementpoint and/or angle, or the component pads are subject to interferencefrom other components, wiring foils, or vias that have already beenplaced, unit 1300 searches in a predetermined area around the placementpoint and angle determined by amendment for a placement point and/orangle that does not result in interference.

[0271] Step S210: Unit 1300 searches for a component placement area inwhich the main body area of the component identified by the selectedcomponent ID name (i.e. “IC1”) is included within the recognizedcandidate area.

[0272] As with step s209, this processing operation involves unit 1300firstly using the prior art method to determine the placement point andangle of the component, and then if the main body area of the componentplaced in accordance with the determined placement point and angledeviates outside of the candidate area, unit 1300 amends the placementarea in order to eliminate the deviation. If any interference arisesfrom other elements, unit 1300 alters at least one of the placementpoint and angle so as to eliminate the interference.

[0273] Step S211: Unit 1300 searches for a component placement area inwhich the inclusive area of the component identified by the selectedcomponent ID name is included within the recognized candidate area.

[0274] As with step s209, this processing operation involves unit 1300firstly using the prior art method to determine the placement point andangle of the component, and then if the inclusive area of the componentplaced in accordance with the determined placement point and angledeviates outside of the candidate area, unit 1300 amends the placementarea in order to eliminate the deviation. If any interference arisesfrom other elements, unit 1300 alters at least one of the placementpoint and angle so as to eliminate the interference.

[0275] Step S212: Unit 1300 searches for a component placement area inwhich the offset area of the component identified by the selectedcomponent ID name is included within the recognized candidate area.

[0276] As with step s209, this processing operation involves unit 1300firstly using the prior art method to determine the placement point andangle of the component, and then if the offset area of the componentplaced in accordance with the determined placement point and angledeviates outside of the candidate area, unit 1300 amends the placementarea in order to eliminate the deviation. If any interference ariseswith other elements, unit 1300 alters at least one of the placementpoint and angle so as to eliminate the interference.

[0277] Step S213: If in any of the searches conducted in steps s209through s212, a component placement area that eliminates deviationoutside the candidate area and interference from other elements cannotbe found, unit 1300 proceeds to the step s216.

[0278] Step S214: Unit 1300 generates component placement informationthat includes the placement point and angle determined or amended as aresult of any of the searches.

[0279] Step S215: Unit 1300 stores the generated component placementinformation in table 450 (FIG. 11).

[0280] Step S216: Unit 1300 judges whether placement of the componentidentified by the selected component ID name is possible.

[0281] Step S217: Unit 1300 repeats the processing operations from steps201 with respect to component ID names specified in the parameters buthaving yet to undergo processing.

[0282] Wiring Processing

[0283] Wiring unit 1400 is mobilized by control unit 1020 when theinformation acquired by input unit 1010 shows a wiring command. In thiscase, unit 1400 receives from control unit 1020 the parameters includedin the command information, and executes the component placementprocessing based on the received parameters.

[0284] In FIG. 2, cell 208 shows exemplary parameters transferred tounit 1400 by control unit 1020. The transferred parameters include oneor more net ID names.

[0285]FIG. 21 is a flowchart of the wiring processing subroutine.

[0286] Step S301: Wiring unit 1400 selects one of the net ID namesspecified in the parameters.

[0287] Step S302: Unit 1400 searches table 440 (FIG. 10) for netinformation that includes the selected net ID name. Unit 1400 alsosearches for a frequency greater than or equal to the first threshold, arise time less than or equal to the second threshold, and a fall timeless than or equal to the third threshold.

[0288] The first, second, and third threshold are provided in advance todesign aiding apparatus 1000 from an external source, and stored in amemory unit (not shown in the drawings).

[0289] If net information is not retrieved from the search, unit 1400proceeds to step s314.

[0290] Step S303: Unit 1400 searches table 460 (FIG. 12) for foilplacement information in which the form type is given as “plane”.

[0291] Step S304: If foil placement information showing “plane” is notretrieved from the search, unit 1400 proceeds to step s305.

[0292] Step S305: Unit 1400 assumes that the form type is “plane” andthat foil placement information showing the coordinates of a placementarea of the plane (i.e. within an area of the wiring board surfaceexcluding a perimeter area having a predetermined margin) was retrievedfrom the search of table 460.

[0293] The coordinates of the placement area of the plane shown in theassumed foil placement information are calculated as follows. Unit 1400acquires the coordinates of the board stored in structural point column401 of board information table 400 (FIG. 6). Unit 1400 also acquires,from clearance information table 480 (FIG. 27) as the predeterminedmargin, the clearance value to be maintained between the wiring foil andthe edge of the board. Unit 1400 then shifts, by an amount equal to theacquired clearance value, the points of the acquired coordinates to bewithin an area marked by lines connecting each of the acquiredcoordinate points, and calculates the coordinates of the shifted points.The calculated coordinates show the vertices of the placement area ofthe plane.

[0294] Step S306: Unit 1400 acquires from table 440 (FIG. 10) netinformation corresponding to the selected net ID name.

[0295] If the wiring foil and via pad clearance values are not specifiedin the acquired net information, unit 1400 acquires the relevantclearance values from plane clearance information table 490 (FIG. 14).

[0296] Unit 1400 then shifts, by an amount equal to the acquired wiringfoil clearance value, the points of the coordinates included in the foilplacement information retrieved in step s303 or assumed to have beenretrieved in step S305 to be within an area marked by lines connectingeach of the points, and calculates the coordinates of the shiftedpoints. Unit 1400 recognizes the area marked by lines connecting each ofthe calculated points as the wiring foil candidate area.

[0297] Unit 1400 also shifts, by an amount equal to the acquired via padclearance value, the points of the coordinates included in the foilplacement information retrieved in step s303 or assumed to have beenretrieved in step S305 to be within an area marked by lines connectingeach of the points, and calculates the coordinates of the shiftedpoints. Unit 1400 recognizes the area marked by lines connecting each ofthe calculated points as the via candidate area.

[0298] Step S307: Unit 1400 determines the placement area of wiringfoils and vias connected to the pins of the component identified by thepin ID name shown in the acquired net information.

[0299] This processing operation may, for example, be conducted asfollows. Firstly, unit 1400 applies the prior art method to determinethe placement area of the wiring foils and vias. Here, the determinedplacement areas satisfy the clearance values shown in table 480 (FIG.27), although no consideration has been given to the margin between thewiring foil/via placement areas and the edge of the plane.

[0300] Next, unit 1400 judges whether the pads of the wiring foils andvias placed in the determined placement areas are included within therecognized wiring foil and via candidate areas, respectively.

[0301] If judged in the negative, unit 1400 calculates the size in theXY direction of the section deviating from the wiring foil and viacandidate areas, and amends the respective placement areas so as toeliminate the deviation.

[0302] If the wiring foils and/or vias placed in amended placement areasare subject to interference from other components, wiring foils, or viasalready placed, unit 1400 searches in a predetermined area around theamended placement area/s for placement area/s that do not result ininterference.

[0303] Step S308: If a placement area is located that eliminates bothderivation of the wiring foils and via pads and interference from otherelements, unit 1400 proceeds to step s311.

[0304] Step S309: Unit 1400 judges whether the overlap between thewiring foil placement and a perimeter area of the plane excluding thewiring foil candidate area from the plane placement area retrieved orassumed to have been retrieved, is small enough to satisfy apredetermined condition. If judged in the negative, unit 1400 searchesfor a placement area that satisfied the predetermined condition and doesnot result in interference from other elements.

[0305] The judgment by unit 1400 can be conducted, for example, in termsof whether or not the centerline of the wiring foil placement area cutsthe perimeter area of the plane orthogonally. As shown in FIG. 24A, ifwiring foils 551 and 552 deviate outside the wiring foil candidate areas553 and 554, respectively, so as to be placed within the perimeter areas555 and 556, respectively, of the plane, unit 1400 can judge in thenegative and alter placement areas 552 and 553 to alternative placementareas 557 and 558, respectively, such that, as shown in FIG. 24B, thecenterline of alternative placement area 558 cuts perimeter area 556orthogonally and the centerline of alternative placement area 557 doesnot cut perimeter area 555 at all.

[0306] Step S310: If placement area/s cannot be found in which theoverlap with the perimeter area of the plane is small enough to satisfythe predetermined condition and in which no interference arises fromother elements, unit 1400 proceeds to step s313.

[0307] Step S311: Unit 1400 generates foil placement information markedas the form type “line” (i.e. routing information) and via placementinformation, which show respectively the placement area of the wiringfoils and vias determined in one of steps s307 and s309.

[0308] Step S312: Unit 1400 stores the generated foil placement and viaplacement information in tables 460 (FIG. 12) and 470 (FIG. 13),respectively.

[0309] Step S313: Unit 1400 judges whether it is possible to place thewiring foils and vias belonging to the net identified by the selectednet ID name.

[0310] Step S314: Unit 1400 repeats the processing operations from steps301 with respect to net ID names specified in the parameters but havingyet to undergo processing.

[0311] Component Placement Inspection Processing

[0312] Component placement inspection unit 1500 is mobilized by controlunit 1020 when the information acquired by input unit 1010 shows acomponent placement inspection command. In this case, unit 1500 receivesfrom control unit 1020 the parameters included in the commandinformation, and executes the component placement inspection processingbased on the received parameters.

[0313] In FIG. 2, cell 209 shows exemplary parameters transferred tounit 1500 by control unit 1020. The transferred parameters include inthe stated order, the area type, and one or more component ID names. Thearea type of the component pad area, the main body area, the inclusivearea, and the offset area is specified using the numbers 1, 2, 3, and 4,respectively.

[0314]FIG. 22 is a flowchart of the component placement inspectionprocessing subroutine.

[0315] Step S401: Component placement inspection unit 1500 selects oneof the component ID names specified in the parameters.

[0316] Step S402: Unit 1500 searches table 440 (FIG. 10) for netinformation showing the pin ID names corresponding to the selectedcomponent ID name. Unit 1500 also retrieves from table 440, netinformation showing a frequency greater than or equal to a firstthreshold, a rise time less than or equal to a second threshold, and afall time less than or equal to a third threshold.

[0317] The first, second, and third threshold are provided in advance todesign aiding apparatus 1000 from an external source, and stored in amemory unit (not shown in the drawings).

[0318] Step S403: If net information is not retrieved from the search oftable 440, unit 1500 proceeds to step s415.

[0319] Step S404: On the other hand, if net information is retrieved,unit 1500 searches table 460 (FIG. 12) for foil placement informationshowing the form type as “plane”.

[0320] Step S405: If foil placement information showing “plane” is notretrieved from the search, unit 1500 proceeds to step s406.

[0321] Step S406: Unit 1500 assumes that the form type is “plane” andthat foil placement information showing the coordinates of a placementarea of the plane (i.e. within an area of the wiring board surfaceexcluding a perimeter area having a predetermined margin) was retrievedfrom the search of table 460. The calculation of the coordinates of theplacement area of the plane is the same as in step s206.

[0322] Step S407: Unit 1500 acquires from table 430 (FIG. 9) componentinformation corresponding to the selected component ID name.

[0323] Depending on whether the area type specified in the parameter is1, 2, 3, or 4, unit 1500 then selects, respectively, the component padclearance value, the component clearance value, the inclusive areaclearance value, or the offset area clearance value included in theacquired component information.

[0324] If the relevant clearance values are not specified in theacquired component information, unit 1500 acquires clearance values fromtable 490 (FIG. 14) and selects the clearance value corresponding to thearea type specified in the parameters.

[0325] Unit 1500 then shifts, by an amount equal to the selectedclearance value, the points of either the coordinates included in theretrieved foil placement information or the coordinates calculated instep S406 to be within an area marked by lines connecting each of thepoints, and calculates the coordinates of the shifted points. Unit 1500recognizes the area marked by lines connecting each of the calculatedpoints as the candidate area of the, component.

[0326] Step S408: Depending on the area type included in the parameter,unit 1500 executes one of steps s409, s410, s411, and s412.

[0327] Step S409: Unit 1500 acquires from table 450 (FIG. 11) componentplacement information corresponding to the selected component ID name.If the component has been placed in accordance with the placement pointand angle included in the acquired component placement information, unit1500 judges whether the component pad area of the component is includedwithin the candidate area. If judged in the affirmative, unit 1500proceeds to step s415.

[0328] Step S410: Unit 1500 acquires from table 450 component placementinformation corresponding to the selected component ID name. If thecomponent has been placed in accordance with the placement point andangle included in the acquired component placement information, unit1500 judges whether the main body area of the component is includedwithin the candidate area. If judged in the affirmative, unit 1500proceeds to step s415.

[0329] Step S411: Unit 1500 acquires from table 450 component placementinformation corresponding to the selected component ID name. If thecomponent has been placed in accordance with the placement point andangle included in the acquired component placement information, unit1500 judges whether the inclusive area of the component is includedwithin the candidate area. If judged in the affirmative, unit 1500proceeds to step s415.

[0330] Step S412: Unit 1500 acquires from table 450 component placementinformation corresponding to the selected component ID name. If thecomponent has been placed in accordance with the placement point andangle included in the acquired component placement information, unit1500 judges whether the offset area of the component is included withinthe candidate area. If judged in the affirmative, unit 1500 proceeds tostep s415.

[0331] Step S413: If judged in the negative, unit 1500 generates designcondition violation information showing the area type included in theparameters and selected component ID name.

[0332] Step S414: Unit 1500 stores the generated design conditionviolation information in table 510 (FIG. 16).

[0333] Step S415: Unit 1500 repeats the processing operations from steps401 with respect to component ID names specified in the parameters buthaving yet to undergo processing.

[0334] Wiring Inspection Processing

[0335] Wiring inspection unit 1600 is mobilized by control unit 1020when the information acquired by input unit 1010 shows a wiringinspection command. In this case, unit 1600 receives from control unit1020 the parameters included in the command information, and executesthe wiring inspection processing based on the received parameters.

[0336] In FIG. 2, cell 210 shows exemplary parameters transferred tounit 1600 by control unit 1020. The transferred parameters include oneor more net ID names.

[0337]FIG. 23 is a flowchart of the wiring inspection processingsubroutine.

[0338] Step S501: Wiring inspection unit 1600 selects one of the net IDnames specified in the parameters.

[0339] Step S502: Unit 1600 searches table 440 (FIG. 10) for netinformation corresponding to the selected net ID name. Unit 1300 alsoretrieves from table 440, net information showing a frequency greaterthan or equal to a first threshold, a rise time less than or equal to asecond threshold, and a fall time less than or equal to a thirdthreshold.

[0340] The first, second, and third threshold are provided in advance todesign aiding apparatus 1000 from an external source and stored in amemory unit (not shown in the drawings).

[0341] If net information is not retrieved from the search of table 440,unit 1600 proceeds to step s512.

[0342] Step S503: On the other hand, if net information is retrieved,unit 1600 searches table 460 (FIG. 12) for foil placement information inwhich the form type is given as “plane”.

[0343] Step S504: If foil placement information showing “plane” is notretrieved from the search, unit 1600 proceeds to step s505.

[0344] Step S505: Unit 1600 assumes that the form type is “plane” andthat foil placement information showing the coordinates of a placementarea of the plane (i.e. within an area of the wiring board surfaceexcluding a perimeter area having a predetermined margin) was retrievedfrom the search of table 460. The calculation of the coordinates of theplacement area of the plane is the same as in step s305.

[0345] Step S506: Unit 1600 acquires from table 440 (FIG. 10) netinformation corresponding to the selected net ID name.

[0346] If the wiring foil and via pad clearance values are not specifiedin the acquired net information, unit 1600 acquires the relevantclearance values from plane clearance information table 490 (FIG. 14).

[0347] Unit 1600 then shifts, by an amount equal to the acquired wiringfoil clearance value, the points of the coordinates included in the foilplacement information retrieved in step s503 or assumed to have beenretrieved in step S505 to be within an area marked by lines connectingeach of the points, and calculates the coordinates of the shiftedpoints. Unit 1600 recognizes the area marked by lines connecting each ofthe calculated points as the wiring foil candidate area.

[0348] Unit 1600 also shifts, by an amount equal to the acquired via padclearance value, the points of the coordinates included in the foilplacement information retrieved in step s503 or assumed to have beenretrieved in step S505 to be within an area marked by lines connectingeach of the points, and calculates the coordinates of the shiftedpoints. Unit 1600 recognizes the area marked by lines connecting each ofthe calculated points as the via candidate area.

[0349] Step S507: Unit 1600 searches table 460 (FIG. 12) for routinginformation corresponding to the selected net ID name and showing thesection of the wiring foil placement area deviating outside the wiringfoil candidate area. If the relevant routing information is notretrieved from the search, unit 1600 proceeds to step s510.

[0350] Step S508: Unit 1600 judges whether the overlap between theplacement area/s shown in the retrieved one or more pieces of routinginformation and a perimeter area of the plane excluding the wiring foilcandidate area from the plane placement area retrieved or assumed tohave been retrieved, is small enough to satisfy a predeterminedcondition.

[0351] The judgment by unit 1600 can be conducted, for example, in termsof whether or not the centerline of the wiring foil placement areaintersects the perimeter area of the plane orthogonally.

[0352] If judged that the predetermined condition is satisfied for allof the retrieved pieces of routing information, unit 1600 proceeds tostep s510.

[0353] Step S509: Unit 1600 generates (i) design condition violationinformation that includes one or more foil ID names showing the wiringfoils judged not to satisfy the predetermined condition, and (ii) a nameshowing “wiring foil” as the area type of the target element. Unit 1600then stores the generated design condition violation information intable 510 (FIG. 16).

[0354] Step S510: Unit 1600 searches table 470 (FIG. 13) for viaplacement information corresponding to the selected net ID name andshowing the section of the via placement area deviating outside the viacandidate area. If the relevant via placement information is notretrieved from the search, unit 1600 proceeds to step s512.

[0355] Step S511: If the relevant via placement information isretrieved, unit 1600 generates design condition violation informationshowing the ID name and element name of the one or more viascorresponding to the retrieved information, and stores the generateddesign condition violation information in table 510 (FIG. 16).

[0356] Step S512: Unit 1600 repeats the processing operations from steps501 with respect to net ID names specified in the parameters but havingyet to undergo processing.

[0357] Variations

[0358] Although described in terms of the above embodiment, the presentinvention is by no means limited to this embodiment, and may include thefollowing variations.

[0359] (1) The invention may be a method that includes, as steps, theprocessing described in the embodiment. Furthermore, the invention maybe a computer program executed by a computer system to realize a designaiding apparatus applying the method, or the invention may be a digitalsignal that expresses the computer program.

[0360] Alternatively, the invention may be a computer-readable storagemedium, such as a flexible disc, a hard disk, a CD-ROM, an MO, a DVD, aDVD-ROM, a DVD-RAM, or a semi-conductor memory, which stores thecomputer program or the digital signal.

[0361] Alternatively, the computer program or the digital signal may betransmitted via a network such as a telecommunications circuit, awireless communications circuit, a cable communications circuit, or theInternet.

[0362] The invention may also be a computer system that includes amicroprocessor and memory. Here, the memory may store the computerprogram, and the method may be realized by the microprocessor operatingin accordance with the computer program stored in the memory.

[0363] Alternatively, the computer program or the digital signal may besent, either stored on the storage medium or via the network, to anindependent computer system which then implements the computer programor digital signal.

[0364] (2) The plane clearance information may be calculated in advanceusing simulation, and then provided to and stored in the design aidingapparatus of the present invention.

[0365] (3) The plane clearance information may be regulated separatelyfor each wiring surface. FIG. 25 shows an exemplary plane clearanceinformation table 520 used in this variation of the invention.

[0366] In table 520, rows 521 to 527 show, respectively, a targetsurface, a component pad clearance value, a component clearance value,an inclusive area clearance value, an offset area clearance value, awiring foil clearance value, and a via pad clearance value.

[0367] Row 521 stores wiring surface numbers showing two wiring surfacesfor each column. When the plane is placed on one of the wiring surfacesshown in one of the columns of row 521, rows 522 to 527 store themargins allowable between the edge of the plane and, respectively, thecomponent pad area, the main body area, the inclusive area, the offsetarea, the wiring foil, and the via pad placed on the other surface.

[0368] (4) In case of plural pieces of foil placement informationshowing the form type as “plane” being retrieved from the search oftable 460 (FIG. 12), the candidate area of a component, wiring foil, orvia targeted for placement may be calculated based on the placement areaof the plane positioned on a wiring surface closest to the wiringsurface on which the component, wiring foil, or via is to be placed. Theplacement area of the component, wiring foil, or via can then bedetermined such that it is included within the calculated candidatearea.

[0369] (5) In case of plural pieces of foil placement informationshowing the form type as “plane” being retrieved from the search oftable 460 (FIG. 12), the candidate area of a component, wiring foil, orvia targeted for placement may be calculated based on the combined areaof all the planes shown in the retrieved information. The placement areaof the component, wiring foil, or via may then be determined such thatit is included within the calculated candidate area.

[0370] This variation is shown in FIG. 26. FIG. 26 shows two planes 531and 532 placed so as to avoid wiring foil 530. Because the candidatearea of the component, wiring foil, or via is calculated, according tothe this variation, based on an area 533 that encompasses both planes531 and 532, the shaded area 534 in FIG. 26 is added to the respectivecandidate areas calculated as described in the embodiment of theinvention.

[0371] By sacrificing a little of the effectiveness of the EMI reductionmeasures, it becomes possible to mitigate placement restrictionsregarding components, wiring foils, and vias, and increase the placementdensity on the wiring board.

[0372] (6) The planes included in the calculation of the componentcandidate area may be restricted to the ground and power planessupplying power to the component. Furthermore, the planes included inthe calculation of the wiring foil and via candidate areas may berestricted to the ground and the power planes supplying power to thecomponent to which the wiring foil and via are connected.

[0373] In particular, a ground plane and a wiring foil placed in acandidate area based on the placement area of the ground plane form amicro strip line, and consequently it is possible to achieve, inaddition to EMI reductions, reductions in transmission loss andincreases in noise tolerance.

[0374] (7) Wiring foils may be placed on a wiring surface sandwichedbetween two ground planes in an area of the ground planes excluding aperimeter area as seen in the lamination direction of the board.

[0375] According to this variation, a strip line is formed by the wiringfoil and the two ground planes, and in comparison to the micro stripline formation it is possible to realize further increases in EMIreduction as well as the reductions in transmission loss and increasesin noise tolerance.

[0376] Although the present invention has been fully described by way ofexamples with reference to the accompanying drawings, it is to be notedthat various changes and modifications will be apparent to those skilledin the art. Therefore, unless such changes and modifications depart fromthe scope of the present invention, they should be construed as beingincluded therein.

What is claimed is:
 1. A design aiding apparatus for aiding in a layout design of an element on a multilayer wiring board, wherein the apparatus determines, when a placement area of a plane foil has been determined, a placement area of the element such that the element, as seen in a lamination direction of the board, is included within an area of the plane foil excluding a perimeter area.
 2. The apparatus of claim 1, wherein a component and a pad, whose placement area is determined relative to a placement area of the component, are included as elements, and the apparatus comprises: plane foil placement information storage means for storing plane foil placement information showing a placement area of a plane foil whose placement area has been determined; plane clearance information acquisition means for acquiring plane clearance information showing one or more margins; and component placement information generation means for determining the placement area of the component such that at least one of the component and the pad, as seen in the lamination direction of the board, is included within a first candidate area of the plane foil excluding a perimeter area having a first margin shown in the plane clearance information, and for generating component placement information showing the determined placement area of the component.
 3. The apparatus of claim 2, further comprising: signal attribute information acquisition means for acquiring signal attribute information showing an abruptness of a change over time of a signal transmitted from or received by the component, wherein the component placement information generation means includes an abruptness judgment unit for judging, based on the signal attribute information, whether the abruptness of the change over time of the signal satisfies a predetermined condition, and generates component placement information only when the abruptness judgment unit judges in the affirmative.
 4. The apparatus of claim 3, wherein the signal attribute information shows at least one of a frequency, a rise time, and a fall time of the signal, and the abruptness judgment unit judges in the affirmative if the frequency of the signal is greater than or equal to a first threshold, or if at least one of the rise time and the fall time of the signal is less than or equal to a second threshold and a third threshold, respectively.
 5. The apparatus of claim 2, wherein an inclusive area has been determined that includes the component and all pads whose placement area is determined relative to the placement area of the component, and the component placement information generation means determines the placement area of the component such that the inclusive area, as seen in the lamination direction of the board, is included within a second candidate area of the plane foil excluding a perimeter area having a second margin shown in the plane clearance information, and generates component placement information showing the determined placement area of the component.
 6. The apparatus of claim 2, wherein the component placement information generation means determines, when plane foil placement information is not stored in the plane foil placement information storage means, the placement area of the component such that at least one of the component and the pad, as seen in the lamination direction of the board, is included within an alternative candidate area of a surface of the board excluding a perimeter area having a predetermined margin, and generates component placement information showing the determined placement area of the component.
 7. The apparatus of claim 1, wherein a wiring foil and a via are included as elements, and the apparatus comprises: plane foil placement information storage means for storing plane foil placement information showing a placement area of a plane foil whose placement area has been determined; plane clearance information acquisition means for acquiring plane clearance information showing one or more margins; wiring foil placement information generation means for determining a placement area of the wiring foil such that the wiring foil, as seen in the lamination direction of the board, is included within a first candidate area of the plane foil excluding a perimeter area having a first margin shown in the plane clearance information, and for generating wiring foil placement information showing the determined placement area of the wiring foil; and via placement information generation means for determining a placement area of the via such that the via, as seen in the lamination direction of the board, is included within a second candidate area of the plane foil excluding a perimeter area having a second margin shown in the plane clearance information, and for generating via placement information showing the determined placement area of the via.
 8. The apparatus of claim 7, further comprising: first signal attribute information acquisition means for acquiring first signal attribute information showing an abruptness of a change over time of a first signal transmitted by the wiring foil; and second signal attribute information acquisition means for acquiring second signal attribute information showing an abruptness of a change over time of a second signal transmitted by the via, wherein the wiring foil placement information generation means includes a first abruptness judgment unit for judging, based on the first signal attribute information, whether the abruptness of the change over time of the first signal satisfies a predetermined condition, and generates component placement information only if the first abruptness judgment unit judges in the affirmative, and the via placement information generation means includes a second abruptness judgment unit for judging, based on the second signal attribute information, whether the abruptness of the change over time of the second signal satisfies a predetermined condition, and generates component placement information only if the second abruptness judgment unit judges in the affirmative.
 9. The apparatus of claim 8, wherein the signal attribute information shows at least one of a frequency, a rise time, and a fall time of the first signal, the first abruptness judgment unit judges in the affirmative if the frequency of the first signal is greater than or equal to a first threshold, or if at least one of the rise time and the fall time of the first signal is less than or equal to a second threshold and a third threshold, respectively, the signal attribute information shows at least one of a frequency, a rise time, and a fall time of the second signal, and the second abruptness judgment unit judges in the affirmative if the frequency of the second signal is greater than or equal to the first threshold, or if at least one of the rise time and the fall time of the second signal is less than or equal to the second threshold and the third threshold, respectively.
 10. The apparatus of claim 7, wherein the wiring foil placement information generation means further includes a wiring possibility judgment unit for judging whether it is possible to determine the placement area of the wiring foil such that the wiring foil, as seen in the lamination direction of the board, is included within the first candidate area, the wiring foil placement information generation means determines, when the wiring possibility judgment unit judges in the affirmative, the placement area of the wiring foil such that the wiring foil, as seen in the lamination direction of the board, is included within the first candidate area, and generates wiring foil placement information showing the determined placement area of the wiring foil, and the wiring foil placement information generation means determines, when the wiring possibility judgment unit judges in the negative, the placement area of the wiring foil such that, as seen in the lamination direction of the board, an overlap between the placement area of the wiring foil and the perimeter area of the plane foil having the first margin is small enough to satisfy a predetermined condition, and generates wiring foil placement information showing the determined placement area of the wiring foil.
 11. The apparatus of claim 7, wherein the wiring foil placement information generation means determines, when plane foil placement information is not stored in the plane foil placement information storage means, the placement area of the wiring foil such that the wiring foil, as seen in the lamination direction of the board, is included within an alternative candidate area of a surface of the board excluding a perimeter area having a predetermined margin, and generates wiring foil placement information showing the determined placement area of the wiring foil, and the via placement information generation means determines, when plane foil placement information is not stored in the plane foil placement information storage means, the placement area of the via such that the via, as seen in the lamination direction of the board, is included within the alternative candidate area, and generates via placement information showing the determined placement area of the via.
 12. The apparatus of claim 7, wherein a component and a pad, whose placement area is determined relative to a placement area of the component, are further included as elements, and the apparatus further comprises: component placement information generation means for determining the placement area of the component such that at least one of the component and the pad, as seen in the lamination direction of the board, is included within a third candidate area of the plane foil excluding a perimeter area having a third margin shown in the plane clearance information, and for generating component placement information showing the determined placement area of the component.
 13. A design aiding apparatus for aiding in a layout design of an element on a multilayer wiring board, wherein the apparatus reports, when a placement area of the element and a plane foil has been determined, a design condition violation if the placement area of the element, as seen in a lamination direction of the board, deviates outside an area of the plane foil excluding a perimeter area.
 14. The apparatus of claim 13, wherein a component, whose placement area has been determined, and a pad, whose placement area is determined relative to the placement area of the component, are included as elements, and the apparatus comprises: component placement information storage means f or storing component placement information showing the placement area of the component; plane clearance information acquisition means for acquiring plane clearance information showing one or more margins; component deviation judgment means for judging, when the component has been placed in accordance with the component placement information, whether the placement area of at least one of the component and the pad, as seen in the lamination direction of the board, deviates outside a first candidate area of the plane foil excluding a perimeter area having a first margin shown in the plane clearance information; and design condition violation information generation means for generating, when the component deviation judgment means judges in the affirmative, component design condition violation information showing the component.
 15. The apparatus of claim 14, further comprising: signal attribute information acquisition means for acquiring signal attribute information showing an abruptness of a change over time of a signal transmitted from or received by the component, wherein the design condition violation information generation means includes an abruptness judgment unit for judging, based on the signal attribute information, whether the abruptness of the change over time of the signal satisfies a predetermined condition, and suppresses the generation of the component design condition violation information when the abruptness judgment unit judges in the negative.
 16. The apparatus of claim 14, wherein an inclusive area has been determined that includes the component and all pads whose placement area is determined relative to the placement area of the component, and the component deviation judgment means judges, when the component has been placed in accordance with the component placement information, whether the inclusive area, as seen in the lamination direction of the board, deviates outside a second candidate area of the plane foil excluding a perimeter area having a second margin shown in the plane clearance information.
 17. The apparatus of claim 14, wherein the component deviation judgment means judges, when plane foil placement information is not stored in the plane foil placement information storage means, whether the placement area of at least one of the component and the pad, as seen in the lamination direction of the board, deviates outside an alternative candidate area of a surface of the board excluding a perimeter area having a predetermined margin.
 18. The apparatus of claim 13, wherein a wiring foil and a via, whose placement areas have been determined, are included as elements, and the apparatus comprises: wiring foil placement information storage means for storing wiring foil placement information showing a placement area of the wiring foil; via placement information storage means for storing via placement information showing a placement area of the via; plane foil placement information storage means for storing plane foil placement information showing a placement area of a plane foil whose placement area has been determined; plane clearance information acquisition means for acquiring plane clearance information showing one or more margins; wiring foil deviation judgment means for judging, when the wiring foil has been placed in accordance with the wiring foil placement information, whether the placement area of the wiring foil, as seen in the lamination direction of the board, deviates outside a first candidate area of the plane foil excluding a perimeter area having a first margin shown in the plane clearance information; via deviation judgment means for judging, when the via has been placed in accordance with the via placement information, whether the placement area of the via, as seen in the lamination direction of the board, deviates outside a second candidate area of the plane foil excluding a perimeter area having a second margin shown in the plane clearance information; and design condition violation information generation means for generating, when the wiring foil deviation judgment means judges in the affirmative, wiring foil design condition violation information showing the wiring foil, and for generating, when the via deviation judgment means judges in the affirmative, via design condition violation information showing the via.
 19. The apparatus of claim 18, further comprising: first signal attribute information acquisition means for acquiring first signal attribute information showing an abruptness of a change over time of a first signal transmitted by the wiring foil; and second signal attribute information acquisition means for acquiring second signal attribute information showing an abruptness of a change over time of a second signal transmitted by the via, wherein the design condition violation information generation means includes a first abruptness judgment unit for judging, based on the first signal attribute information, whether the abruptness of the change over time of the first signal satisfies a predetermined condition; and a second abruptness judgment unit for judging, based on the second signal attribute information, whether the abruptness of the change over time of the second signal satisfies a predetermined condition, and the design condition violation information generation means suppresses the generation of the wiring foil design condition violation information when the first abruptness judgment unit judges in the negative, and suppresses the generation of the via design condition violation information when the second abruptness judgment unit judges in the negative.
 20. The apparatus of claim 18, wherein the design condition violation information generation means suppresses the generation of the wiring foil design condition violation information when the wiring foil deviation judgment means judges in the affirmative, and when the placement area of the wiring foil is such that, as seen in the lamination direction of the board, an overlap between the placement area of the wiring foil and the perimeter area of the plane foil having the first margin is small enough to satisfy a predetermined condition.
 21. The apparatus of claim 18, wherein the wiring foil deviation judgment means judges, when plane foil placement information is not stored in the plane foil placement information storage means, whether the placement area of the wiring foil, as seen in the lamination direction of the board, deviates outside an alternative candidate area of a surface of the board excluding a perimeter area having a predetermined margin, and the via deviation judgment means judges, when plane foil placement information is not stored in the plane foil placement information storage means, whether the placement area of the via, as seen in the lamination direction of the board, deviates outside an alternative candidate area of a surface of the board excluding a perimeter area having a predetermined margin.
 22. The apparatus of claim 18, wherein a component, whose placement area has been determined, and a pad, whose placement area is determined relative to the placement area of the component, are further included as elements, the apparatus further comprises: component placement information storage means for storing component placement information showing the placement area of the component; and component deviation judgment means for judging, when the component has been placed in accordance with the component placement information, whether the placement area of at least one of the component and the pad, as seen in the lamination direction of the board, deviates outside a third candidate area of the plane foil excluding a perimeter area having a third margin shown in the plane clearance information, and the design condition violation information generation means generates, when the component deviation judgment means judges in the affirmative, component design condition violation information showing the component.
 23. A design aiding method for aiding in a layout design of an element on a multilayer wiring board, comprising: a plane clearance information acquisition step of acquiring plane clearance information showing one or more margins; and a placement information generation step of determining, when a placement area of a plane foil has been determined, a placement area of the element such that the element, as seen in a lamination direction of the board, is included within a candidate area of the plane foil excluding a perimeter area having a margin shown in the plane clearance information, and of generating placement information showing the determined placement area of the element.
 24. A design aiding method for aiding in a layout design of an element on a multilayer wiring board, comprising: a plane clearance information acquisition step of acquiring plane clearance information showing one or more margins; and a design condition violation information reporting step of reporting, when a placement area of the element and a plane foil has been determined, a design condition violation if the placement area of the element, as seen in a lamination direction of the board, deviates outside a candidate area of the plane foil excluding a perimeter area having a margin shown in the plane clearance information.
 25. A computer program executed by a design aiding apparatus that aids in a layout design of an element on a multilayer wiring board, including: a plane clearance information acquisition step of acquiring plane clearance information showing one or more margins; and a placement information generation step of determining, when a placement area of a plane foil has been determined, a placement area of the element such that the element, as seen in a lamination direction of the board, is included within a candidate area of the plane foil excluding a perimeter area having a margin shown in the plane clearance information, and of generating placement information showing the determined placement area of the element.
 26. A computer program executed by a design aiding apparatus that aids in a layout design of an element on a multilayer wiring board, including: a plane clearance information acquisition step of acquiring plane clearance information showing one or more margins; and a design condition violation information reporting step of reporting, when a placement area of the element and a plane foil has been determined, a design condition violation if the placement area of the element, as seen in a lamination direction of the board, deviates outside a candidate area of the plane foil excluding a perimeter area having a margin shown in the plane clearance information.
 27. A computer-readable storage medium storing a computer program executed by a design aiding apparatus that aids in a layout design of an element on a multilayer wiring board, the computer program including: a plane clearance information acquisition step of acquiring plane clearance information showing one or more margins; and a placement information generation step of determining, when a placement area of a plane foil has been determined, a placement area of the element such that the element, as seen in a lamination direction of the board, is included within a candidate area of the plane foil excluding a perimeter area having a margin shown in the plane clearance information, and of generating placement information showing the determined placement area of the element.
 28. A computer-readable storage medium storing a computer program executed by a design aiding apparatus that aids in a layout design of an element on a multilayer wiring board, the computer program including: a plane clearance information acquisition step of acquiring plane clearance information showing one or more margins; and a design condition violation information reporting step of reporting, when a placement area of the element and a plane foil has been determined, a design condition violation if the placement area of the element, as seen in a lamination direction of the board, deviates outside a candidate area of the plane foil excluding a perimeter area having a margin shown in the plane clearance information. 